The present invention relates to a method and apparatus for verifying the maximum allowable load of a logic macro-cell that is required to design a semiconductor integrated circuit.
A semiconductor integrated circuit is typically composed of a plurality of logic macro-cells. A logic macro-cell refers to a function block that is formed from a combination of basic cells, such as CMOSs and the like. Logic macro-cells include those ranging from basic blocks, such as inverters, NANDs, NORs and the like to high performance blocks, such as flip-flops, counters, adders, decoders, multiplexers and the like. A semiconductor integrated circuit realizes required functions by inputting and outputting signals through the respective logic macro-cells.
To achieve a specified function, a signal that is inputted in a logic macro-cell in a preceding stage needs to be securely transmitted to a logic macro-cell in a succeeding stage such that the logic macro-cell in the succeeding stage operates with its normal function. Accordingly, the maximum allowable load of the logic macro-cell in the preceding stage needs to be verified.
Conventionally, the maximum allowable load of a preceding logic macro-cell is compared with an input capacitance load of a succeeding logic macro-cell, and an error indication is made when the latter exceeds the former.
In recent years, the miniaturization in manufacturing methods for manufacturing semiconductor integrated circuits and the larger scale integration of semiconductor integrated circuits are being progressed. Due to the miniaturized manufacturing process, the line width of wiring becomes thinner. Also, due to the larger scale integration of semiconductor integrated circuits, the number of logic macro-cells to be placed in a single chip increases and the length of wiring increases due to roundabout routing of the wirings. When the line width of wiring narrows and the line length thereof increases, the line resistance increases. Also, an increase in the wiring capacitance cannot be ignored. Furthermore, the hole capacitance at contact holes or via holes cannot be ignored in view of the multiplicity of wiring layers.
Therefore, the mere comparison between the maximum allowable load of a preceding logic macro-cell and an input capacitance load of a succeeding logic macro-cell ignores deteriorating effects of the wiring resistances, wiring capacitances and hole capacitances. Accordingly, this presents a problem in which a simulation result for a semiconductor integrated circuit does not correctly reflect an operation of an actual circuit.
In particular, for a semiconductor integrated circuit that is manufactured by a miniaturized process for a line width of 0.5 xcexcm or less, the resistance value of MOS transistors in the logic macro-cell lowers, with the result that an output impedance of a preceding logic macro-cell 601 (see for example, FIG. 10). becomes small. On the other hand, the wiring resistance of connection nets 620-622 (see for example, FIG. 12) increases. This aggravates the problem described above.
Also, there is an occasion to design semiconductor integrated circuits that have substantially the same placement and wiring scheme, but have different driving conditions. In such a case, library data for each semiconductor integrated circuit that has minor changes needs to be prepared. As a result, a problem arises in that the volume of library data undesirably increases.
Therefore, it is an object of the present invention to provide a method and an apparatus that can perform the verification of a semiconductor integrated circuit with a higher accuracy.
It is another object of the present invention to provide, for a semiconductor integrated circuit in which a logic macro-cell that is subjected to the verification is connected to a plurality of logic macro-cells in succeeding stages, a verification method and a verification apparatus which can readily determine which one of connection nets is attributable to the generation of an error.
It is still another object of the present invention to provide a method and an apparatus that can perform the verification of semiconductor integrated circuits without increasing the volume of library data, when one semiconductor integrated circuit has driving conditions different than those of the other semiconductor integrated circuits.
In accordance with one embodiment of the present invention, a verification method is provided for verifying a semiconductor integrated circuit having a first logic macro-cell to be verified and a second logic macro-cell in which an output from the first logic macro-cell is inputted. The method is characterized in comprising the step of obtaining data that quantitatively represents a blunting of a waveform of a signal that is inputted from the first logic macro-cell to the second logic macro-cell, and the step of converting the data that quantitatively represents a blunting of a waveform of a signal and data for the maximum allowable load that is predetermined for the first logic macro-cell into equivalent conversion values, and comparing the values and outputting a result of the comparison.
In accordance with the above-described embodiment, when the maximum allowable load of the first logic macro-cell is verified, data that quantitatively represents a blunting of a waveform of a signal that is inputted in the second logic macro-cell in a succeeding stage is obtained. Because this data cannot be directly compared with the data for the maximum allowable load of the first logic macro-cell, one or both of the data is converted to equivalent conversion values having their dimensions match one another, and the values are compared. Based on the comparison result, the maximum allowable load of the first logic macro-cell is verified.
In accordance with another embodiment of the present invention, the data that quantitatively represents a blunting of a waveform of a signal that is inputted in the second logic macro-cell is obtained as an input slew rate of a signal that is inputted in the second logic macro-cell from the first logic macro-cell. On the other hand, the maximum allowable load of the first logic macro-cell is set as a conversion slew rate representative of a slew rate of a signal. The conversion slew rate and the input slew rate are compared and a comparison result is outputted, to thereby verify the maximum allowable load of the first logic macro-cell.
In the step of outputting the comparison result, an error can be outputted when the input slew rate exceeds the conversion slew rate. In this case, the second logic macro-cell cannot be operated with its normal function.
In the step of outputting the comparison result, a value for the conversion slew rate and a value of the input slew rate may preferably be outputted together. In particular, when an error occurs, the cause of the error can be quantitatively verified.
The step of obtaining the input slew rate may preferably include the step of obtaining a wiring capacitance value and a wiring resistance value of a connection net that connects the first logic macro-cell and the second logic macro-cell, and the step of obtaining the input slew rate based on the wiring capacitance value and the wiring resistance value of the connection net.
As a result, the accuracy in the verification of the maximum allowable load of the first logic macro-cell is improved. This is important because, in the miniaturized process for processing sub-micron geometry, a blunting of a signal waveform due to the wiring resistance cannot be ignored.
In this case, the step of outputting the comparison result may preferably include the step of outputting the wiring resistance value and/or the wiring capacitance value of the connection net when an error is outputted.
In accordance with still another embodiment of the present invention, a verification method is defined for verifying a semiconductor integrated circuit that has a first logic macro-cell and a plurality of second logic macro-cells in which an output from the first logic macro-cell is inputted. In this case, an input slew rate of a signal inputted in each of the plurality of second logic macro-cells is obtained. A conversion slew rate and each of the input slew rates are compared, and comparison results are outputted, to thereby verify the maximum allowable load of the first logic macro-cell.
In this case, an error may preferably be outputted when at least one of the plurality of input slew rates exceeds the conversion slew rate. In this case, the second logic macro-cell that causes the error cannot be operated with its normal function.
In the step of outputting the comparison results, when errors are outputted, data that specifying all of the second logic macro-cells that cause the errors may also be outputted. As a result, the sources of the errors can be instantaneously determined.
Further, in the step of outputting the comparison results, when errors are outputted, a value for the conversion slew rate and values for the input slew rates of signals that are inputted in all of the second logic macro-cells that cause the errors may preferably be outputted together. Accordingly, the sources of the errors can be quantitatively verified.
The step of obtaining each of the input slew rates includes: the step of obtaining a wiring capacitance value and a wiring resistance value of each of a plurality of connection nets that connect the first logic macro-cell to the plurality of second logic macro-cells, and the step of obtaining each of the input slew rates that are inputted in the plurality of second logic macro-cells based on the wiring capacitance value and the wiring resistance value of each of the plurality of connection nets. As a result, the wiring resistance value that is a dominant factor attributable to the blunt of a signal waveform in the miniature processing for processing a sub-micron geometry is considered, and therefore the maximum allowable load of the first logic macro-cell can be verified with a higher accuracy.
In this case, the step of outputting the comparison results may preferably include the step of outputting wiring resistance values and/or wiring capacitance values of connection nets that connect to all of the second logic macro-cells that cause the errors, when the errors are outputted. By this, causes of the errors can be quantitatively confirmed.
In accordance with the embodiments described above, the step of setting the conversion slew rate may preferably include the step of changing the conversion slew rate that is predetermined for one driving condition based on another driving condition. This can prevent an increase in the amount of the library for the logic macro-cells, which may result from each of such modifications to the driving condition.
In accordance with another embodiment of the present invention, a verification method for verifying a semiconductor integrated circuit that has a first logic macro-cell and a plurality of second logic macro-cells in which an output from the first logic macro-cell is inputted through a plurality of connection nets. The verification method includes:
the step of setting a maximum allowable load of the first logic macro-cell,
the step of obtaining a sum of input loads of the plurality of connection nets and the plurality of second logic macro-cells in which an output from the first logic macro-cell is inputted, and
the step of comparing the maximum allowable load and the sum of input loads and outputting a comparison result,
wherein the step of outputting the comparison result includes outputting an error when the sum of input loads exceeds the maximum allowable load, and outputting a value for the input load of each of the plurality of connection nets and the plurality of the second logic macro-cells.
In accordance with still another embodiment of the present invention, the maximum allowable load of the first logic macro-cell is verified depending on whether or not the sum of input loads of the plurality of connection nets and the plurality of second logic macro-cells exceeds the maximum allowable load of the first logic macro-cell. However, when the errors are outputted, a value for the input load of each of the plurality of connection nets and the plurality of the second logic macro-cells is also outputted. As a result, causes of the errors can be instantaneously recognized and the causes of the errors can be quantitatively recognized.
In accordance with still another embodiment of the present invention, the maximum allowable load of the first logic macro-cell is compared with a sum capacitance of a wiring capacitance of at least one of the connection nets and an input capacitance of at least one of the second logic macro-cells in which an output from the first logic macro-cell is inputted. When the sum capacitance exceeds the maximum allowable load, an error is outputted. In this instance, the wiring capacitance of the connection nets is considered, and therefore the verification accuracy is improved.